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low voltage 1:18 cloc k distribution chip mpc940l idt? / ics? 1:18 clock distribution chip 1 mpc940l rev 7 june 5, 2007 the mpc940l is a 1:18 low voltage clock distribut ion chip with 2.5 v or 3.3 v lvcmos output capabilities. the device features the capability to select either a differential lvpecl or an lvcmos compatible input. th e 18 outputs are 2.5 v or 3.3 v lvcmos compatible and feature the drive strength to drive 50 ? series or parallel terminated transmission lines. with output-to-output skews of 150 ps, the mpc940l is ideal as a clock distribution chip for the most demandi ng of synchronous systems. the 2.5 v outputs also make the device ideal for supplying clocks for a high performance microprocessor based design. for a similar device at a lowe r price/performance poi nt, the reader is referred to the mpc9109. ? lvpecl or lvcmos clock input ? 2.5 v lvcmos outputs for pentium ii microprocessor support ? 150 ps maximum output-to-output skew ? maximum output frequency of 250 mhz ? 32-lead lqfp packaging ? 32-lead pb-free package available ? dual or single supply device: ?dual v cc supply voltage, 3.3 v core and 2.5 v output ? single 3.3 v v cc supply voltage for 3.3 v outputs ? single 2.5 v v cc supply voltage for 2.5 v i/o with a low output impedance ( 20 ? ), in both the high and low logic states, the output buffers of the mpc940l are ideal for dr iving series terminated transmission lines. with a 20 ? output impedance the 940l has the capability of driving two series terminated lines from each output. this gives the device an effective fanout of 1:36. if a lower output impedance is desired please see the mpc942 data sheet. the differential lvpecl inputs of the mpc9 40l allow the device to interface directly with a lvpecl fanout buffer like the mc100ep111 to build very wide clock fanout trees or to couple to a high frequency clock source. the lvcmos input provides a more standard interface for applications requiring o nly a single clock distribution chip at relatively low frequencies. in addition, the two clock sources can be used to provide for a t est clock interface as well as the primary system clock. a logic high on the lvcmos_clk_sel pin will select the lvcmos level clock input. all inputs of the mpc940l have internal pullup/pulldow n resistors so they can be left open if unused. the mpc940l is a single or dual supply device. the device power supply offers a high degree of flexibility. the device can oper ate with a 3.3 v core and 3.3 v output, a 3.3 v core and 2.5 v output s as well as a 2.5 v core and 2.5 v outputs. the 32-lead lqfp package was chosen to optimize performa nce, board space and cost of the device. the 32- lead lqfp has a 7x7 mm body size with a conserva tive 0.8 mm pin spacing. mpc940l low voltage 1:18 clock distribution chip fa suffix 32-lead lqfp package case 873a-04 ac suffix 32-lead lqfp package pb-free package case 873a-04 pentium ii is a trademark of intel corporation.
mpc940l low voltage 1:18 cloc k distribution chip idt? / ics? 1:18 clock distribution chip 2 mpc940l rev 7 june 5, 2007 logic diagram table 1. pin configurations pin i/o type function pecl_clk input lvpecl reference clock input pecl_clk lvcmos_clk input lvcmos alternative reference clock input lvcmos_clk_sel input lvcmos selects clock source q0?q17 output lvcmos clock outputs v cco supply output positive power supply v cci supply core positive power supply gndo supply output negative power supply gndi supply core negative power supply 0 1 16 q0 q1?q16 q17 pecl_clk pecl_clk lvcmos_clk lvcmos_clk_sel (internal pulldown) pinout: 32-lead lqfp (top view) gndo q5 q4 q3 v cco q2 q1 q0 v cco q12 q13 q14 gndo q15 q16 q17 q6 q7 q8 v cci q9 q10 q11 gnd gndo gndi v cci lvcmos_clk lvcmos_clk_sel pecl_clk pecl_clk v cco 25 26 27 28 29 30 31 32 15 14 13 12 11 10 9 12345678 24 23 22 21 20 19 18 17 16 mpc940l function table lvcmos_clk_sel input 0 1 pecl_clk lvcmos_clk power supply voltages supply pin voltage level v cci v cco 2.5 v or 3.3 v 5% 2.5 v or 3.3 v 5%
mpc940l low voltage 1:18 cloc k distribution chip idt? / ics? 1:18 clock distribution chip 3 mpc940l rev 7 june 5, 2007 table 2. absolute maximum ratings (1) 1. absolute maximum continuous ratings are those values beyond wh ich damage to the device may occu r. exposure to these condition s or conditions beyond those indicated may adversely affect device reliability. func tional operation under abs olute-maximum-rated co nditions is not implied. symbol parameter min max unit v cc supply voltage ?0.3 3.6 v v i input voltage ?0.3 v dd + 0.3 v i in input current 20 ma t stor storage temperature range ?40 125 c table 3. dc characteristics (t a = 0 to 70 c, v cci = 3.3 v 5%; v cco = 3.3 v 5%) symbol characteristic min typ max unit condition v ih input high voltage cmos_clk 2.4 v cci v v il input low voltage cmos_clk 0.8 v v pp peak-to-peak input voltage pecl_clk 500 1000 mv v cmr common mode range pecl_clk v cci ? 1.4 v cci ? 0.6 v v oh output high voltage 2.4 v i oh = ?20 ma v ol output low voltage 0.5 v i ol = 20 ma i in input current 200 a c in input capacitance 4.0 pf c pd power dissipation capacitance 10 pf per output z out output impedance 18 23 28 ? i cc maximum quiescent supply current 0.5 1.0 ma table 4. ac characteristics (t a = 0 to 70 c, v cci = 3.3 v 5%; v cco = 3.3 v 5%) symbol characteristic min typ max unit condition f max maximum input frequency 250 mhz t plh propagation delay pecl_clk 150 mhz cmos_clk 150 mhz 2.0 1.8 2.7 2.5 3.4 3.0 ns t plh propagation delay pecl_clk > 150 mhz cmos_clk > 150 mhz 2.0 1.8 2.9 2.4 3.7 3.2 ns t sk(o) output-to-output skew pecl_clk cmos_clk 150 150 ps t sk(pp) part-to-part skew pecl_clk 150 mhz cmos_clk 150 mhz 1.4 1.2 ns note (1) 1. across temperature and voltage ranges. includes output skew. t sk(pp) part-to-part skew pecl_clk > 150 mhz cmos_clk > 150 mhz 1.7 1.4 ns note (1) t sk(pp) part-to-part skew pecl_clk cmos_clk 850 750 ps note (2) 2. for specific temperature and voltage. includes output skew. dc output duty cycle f clk < 134 mhz f clk 250 mhz 45 40 50 50 55 60 % % input dc = 50% input dc = 50% t r , t f output rise/fall time 0.3 1.1 ns 0.5 ? 2.4 v
mpc940l low voltage 1:18 cloc k distribution chip idt? / ics? 1:18 clock distribution chip 4 mpc940l rev 7 june 5, 2007 table 5. dc characteristics (t a = 0 to 70 c, v cci = 3.3 v 5%; v cco = 2.5 v 5%) symbol characteristic min typ max unit condition v ih input high voltage cmos_clk 2.4 v cci v v il input low voltage cmos_clk 0.8 v v pp peak-to-peak input voltage pecl_clk 500 1000 mv v cmr common mode range pecl_clk v cci ? 1.4 v cci ? 0.6 v v oh output high voltage 1.8 v i oh = ?12 ma v ol output low voltage 0.5 v i ol = 12 ma i in input current 200 a c in input capacitance 4.0 pf c pd power dissipation capacitance 10 pf per output z out output impedance 23 ? i cc maximum quiescent supply current 0.5 1.0 ma table 6. ac characteristics (t a = 0 to 70 c, v cci = 3.3 v 5%; v cco = 2.5 v 5%) symbol characteristic min typ max unit condition f max maximum input frequency 250 mhz t plh propagation delay pecl_clk 150 mhz cmos_clk 150 mhz 2.0 1.7 2.8 2.5 3.5 3.0 ns t plh propagation delay pecl_clk > 150 mhz cmos_clk > 150 mhz 2.0 1.8 2.9 2.5 3.8 3.3 ns t sk(o) output-to-output skew pecl_clk cmos_clk 150 150 ps t sk(pp) part-to-part skew pecl_clk 150 mhz cmos_clk 150 mhz 1.5 1.3 ns note (1) 1. across temperature and voltage ranges. includes output skew. t sk(pp) part-to-part skew pecl_clk > 150 mhz cmos_clk > 150 mhz 1.8 1.5 ns note (1) t sk(pp) part-to-part skew pecl_clk cmos_clk 850 750 ps note (2) 2. for specific temperature and voltage. includes output skew. dc output duty cycle f clk < 134 mhz f clk 250 mhz 45 40 50 50 55 60 % % input dc = 50% input dc = 50% t r , t f output rise/fall time 0.3 1.2 ns 0.5 ? 1.8 v
mpc940l low voltage 1:18 cloc k distribution chip idt? / ics? 1:18 clock distribution chip 5 mpc940l rev 7 june 5, 2007 table 7. dc characteristics (t a = 0 to 70 c, v cci = 2.5 v 5%; v cco = 2.5 v 5%) symbol characteristic min typ max unit condition v ih input high voltage cmos_clk 2.0 v cci v v il input low voltage cmos_clk 0.8 v v pp peak-to-peak input voltage pecl_clk 500 1000 mv v cmr common mode range pecl_clk v cci ? 1.0 v cci ? 0.6 v v oh output high voltage 1.8 v i oh = ?12 ma v ol output low voltage 0.5 v i ol = 12 ma i in input current 200 a c in input capacitance 4.0 pf c pd power dissipation capacitance 10 pf per output z out output impedance 18 23 28 ? i cc maximum quiescent supply current 0.5 1.0 ma table 8. ac characteristics (t a = 0 to 70 c, v cci = 2.5 v 5%; v cco = 2.5 v 5%) symbol characteristic min typ max unit condition f max maximum input frequency 200 mhz t plh propagation delay pecl_clk 150 mhz cmos_clk 150 mhz 2.6 2.3 4.0 3.1 5.2 4.0 ns t plh propagation delay pecl_clk > 150 mhz cmos_clk > 150 mhz 2.8 2.3 3.8 3.1 5.0 4.0 ns t sk(o) output-to-output skew pecl_clk cmos_clk 200 200 ps t sk(pp) part-to-part skew pecl_clk 150 mhz cmos_clk 150 mhz 2.6 1.7 ns note (1) 1. across temperature and voltage ranges. includes output skew. t sk(pp) part-to-part skew pecl_clk > 150 mhz cmos_clk > 150 mhz 2.2 1.7 ns note (1) t sk(pp) part-to-part skew pecl_clk cmos_clk 1.2 1.0 ns note (2) 2. for specific temperature and voltage. includes output skew. dc output duty cycle f clk < 134 mhz f clk 200 mhz 45 40 50 50 55 60 % % input dc = 50% input dc = 50% t r , t f output rise/fall time 0.3 1.2 ns 0.5 - 1.8 v
mpc940l low voltage 1:18 cloc k distribution chip idt? / ics? 1:18 clock distribution chip 6 mpc940l rev 7 june 5, 2007 figure 1. lvcmos_clk mpc940l ac test reference for v cc = 3.3 v and v cc = 2.5 v figure 2. pecl_clk mpc940l ac test reference for v cc = 3.3 v and v cc = 2.5 v figure 3. propagation delay (t pd ) test reference figure 4. lvcmos propagation delay (t pd ) test reference figure 5. output duty cycle (dc) figure 6. output-to-output skew t sk(o) figure 7. output transition time test reference figure 8. input transition time test reference pulse generator z = 50 ? r t = 50 ? z o = 50 ? r t = 50 ? z o = 50 ? mpc940l dut v tt v tt differential pulse generator z = 50 ? r t = 50 ? z o = 50 ? r t = 50 ? z o = 50 ? mpc940l dut v tt v tt v cc v cc 2 gnd v pp v cmr pclk_clk pclk_clk q t pd lvcmos_clk q v cc v cc 2 gnd t pd v cc v cc 2 gnd the time from the pll controlled edge to the non controlled edge, divided by the time between pll controlled edges, expressed as a percentage. dc = t p /t 0 x 100% v cc v cc 2 gnd t 0 t p the pin-to-pin skew is defined as the worst case difference in propagation delay between any two similar delay paths within a single device. t sk(o) v cc 2 gnd v oh v cc 2 gnd v cc t f t r v cc = 3.3 v v cc = 2.5 v 2.4 0.55 1.8 v 0.6 v t f t r v cc = 3.3 v v cc = 2.5 v 2.0 0.8 1.7 v 0.7 v
mpc940l low voltage 1:18 clock distribution chip idt? / ics? 1:18 clock distribution chip 7 mpc940l rev 7 june 5, 2007 package dimensions case 873a-04 issue c 32-lead lqfp package page 1 of 3
mpc940l low voltage 1:18 cloc k distribution chip idt? / ics? 1:18 clock distribution chip 8 mpc940l rev 7 june 5, 2007 package dimensions case 873a-04 issue c 32-lead lqfp package page 2 of 3
mpc940l low voltage 1:18 cloc k distribution chip idt? / ics? 1:18 clock distribution chip 9 mpc940l rev 7 june 5, 2007 package dimensions case 873a-04 issue c 32-lead lqfp package page 3 of 3
mpc940l low voltage 1:18 cloc k distribution chip idt? / ics? 1:18 clock distribution chip 10 mpc940l rev 7 june 5, 2007 ordering information table 9. ordering information part/order number marking package shipping packaging termperature mpc940lfa mpc940l 32 lead lqfp tray 0c to 70c MPC940LFAR2 mpc940l 32 lead lqfp 2500 tape & reel 0c to 70c mpc940lac mpc940lac lead-free, 32 lead lqfp tray 0c to 70c mpc940lacr2 mpc940lac lead-free, 32 lead lqfp 2500 tape & reel 0c to 70c
mpc940l low voltage 1:18 cloc k distribution chip ? 2006 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other brands, product names a nd marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa corporate headquarters integrated device technology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800 345 7015 +408 284 8200 (outside u.s.) asia pacific and japan integrated device technology singapore (1997) pte. ltd. reg. no. 199707558g 435 orchard road #20-03 wisma atria singapore 238877 +65 6 887 5505 europe idt europe, limited 321 kingston road leatherhead, surrey kt22 7tu england +44 (0) 1372 363 339 fax: +44 (0) 1372 378851 for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support netcom@idt.com 480-763-2056 innovate with idt and accelerate your future netw orks. contact: www.idt.com

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